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| INDEX MX86250 THE ADVANCED 64-BIT WINDOWS-95 AND DIRECTDRAW ACCELERATOR 1. INTRODUCTION The MX86250 is a new generation of fully integrated graphics and video accelerator. On a single chip, it integrates a 64-bit graphics CoProcessor, a true-color video processor, 135 MHz RAMDAC and dual programmable clock synthesizer. The MX86250 not only delivers extreme high performance in conventional GUI acceleration, it also provides very rich functionality for motion video applications. The MX86250 true color video processor allows full screen full motion playback of AVI and MPEG video from software based Codec's such as MPEG, Cinepak and Indeo. For even higher quality MPEG video playback, the MX86250 Media port supports the VMI connector linking to an external MPEG-1 decoder chip. The Media port also provides for playback and capture of live video input from TV tuner or video camera. One key design goal of the MX86250 is to achieve the highest possible memory bandwidth in the display memory subsystem using main stream and cost effective EDO DRAM chips. By applying the RISC design technique of super pipelining, the MX86250 graphics CoProcessor can execute one bitblt operation in every clock cycle. When running at 50 Mhz and above, using 50 or faster EDO DRAM ( 20ns page mode cycle time), the bandwidth can reach 400 MB/sec and above. This extremely high bandwidth gives top-notch Windows GUI performance and fast frame rate in motion video playback. For mainstream software Codec delivered video playback, the MX86250 provides video acceleration by a second generation" video processor consisting of YUV to RGB converter, scaler, and two dimensional bilinear filter. The scaler can zoom the video windows at arbitrary ratios. The bilinear filter provides both horizontal and vertical interpolation which is absent from 1st generation video chips. For Windows 95 Games, the MX86250 supports DirectDraw with a rich set of features such as fast transparent Blts, double buffering and page flipping so that Windows 95 based games can achieve high speed sprite animation. 1.1 FEATURES High Performance 64 bit Graphics CoProcessor * Uniformly accelerated graphics operations in all pixel formats : 256 color, High color and True color * Optimized graphics engine for BitBLTs, rectangle fill, pattern fill, line draw, color expansion, text transfer, and clipping * Raster Operations (ROPs) with 3 operand BitBLT ALU * One chip 8x8x24 pattern memory achieves highest thrughput in the most common BitBLT in Windows-- the Pattern BLT * Deep on-chip Source and Destination FIFOs for sus tained burst cycles in BitBLTs * Double buffered CoProcessor registers allows concur rent processing with CPU * Built in Hardware cursor Extremely high bandwidth * Achieves single clock cycle DRAM access in Graphics Processor, Video Processor and Display Processor P/N:PM0387 * Provides 400 MB/sec memory bandwidth using -50 EDO DRAM chips * Even higher performance can be achieved by using 35 EDO DRAM for 533 MB/sec bandwidth which is comparable to synchronous DRAM Fully Integrated for Lower system cost * Integrated 24 bit True Color RAMDAC supports 135 Mhz pixel rate and 256x18 look-up table with High Color and True color bypass mode support * Integrated dual clock synthesizers * Glueless PCI local bus interface * Two wire interface to EEPROM, VESA DDC inter face or I2C channel Flexible Display Memory configuration * 1,2, or 4 MB display memory. * 256K x 4, 256K x 8, and 256K x 16 dual CAS or dual WE DRAM. * Fast-page and Hyper-page EDO REV. 1.1, JUL 26, 1996 1 INDEX MX86250 Motion Video Codec Acceleration * YUV/YCrCb conversion of industry standard YUV 4.2.2 or 2.1.1 formats * Non-integer zoom in both X and Y direction * Interpolation with Bi-linear filters in both Horizontal and Vertical dimensions * Color Key supports video overlay, Chroma key sup ports transparency effect or blue screen video * Edge Blending for smooth looking Blue screen video * Video window is double buffered for smooth video play back. * Independent video window mode allowing true-color video, independent of graphics color depth. Windows 95 Game acceleration * Designed to accelerate Windows 95 DirecDraw for game acceleration * Fast Transparent BitBLT for sprite animation * Linear access to offscreen DirectDraw surface storing multiple sprites * Double buffer to support page flipping which is syn chronized to vertical retrace Media Port interface to MPEG decoder chips or Video Capture frontend * Glueless interface to VMI (Video Module Interface) connector to allow plug-in daughtercard of hardware MPEG-1 support * Glueless interface to Phillips 7110 for live video input * Dual aperture for simultaneous access to display memory from Graphics and Video * Built in FIFO and flexible decimator High speed PCI local bus * Support zero wait state PCI burst cycles for maximum CPU write bandwidth * Support version 2.1 PCI disconnect and retry cycles to free CPU from status polling overhead * level command and data FIFO Unified Memory Architecture (UMA) support * Support VESA UMA (VUMA) standard * Programmable wait states in DRAM access cycles to work with slower main memory DRAM chips * DRAM interface buffers have programmable drive strength for optimal power versus performance tradeoff * VESA Display Data Channel (DDC-2B) protocol support * Two wire EEPROM interface * I2C channel * VESA standard and advanced Feature Connector (VAFC) Support * General purpose I/O pins Complete Hardware compatibility * Windows 95 Plug and Play compliant * VGA Hardware, register, and BIOS compatible * PCI revision 2.1 compatible Low-Power 0.5 um CMOS technology Extended Display Resolution support * 1600x1200, 64K color (int) * 1280x1024, 64K color @ 75 Hz * 1024x768, 16M color @ 60 Hz "Green PC"" power management * Support VESA DPMS (Display Power Management) standard * Built in advanced power management techniques such as internal DAC power down mode and clock idle modes Multiple peripheral interfaces 208 pin PQFP package P/N:PM0387 REV. 1.1, JUL 26, 1996 2 INDEX MX86250 2.Functional Description This chapter describes the architecture and function blocks of te architecturtecture and function blocks of the MX86250. 2.1 Overview The MX86250 architecture is described in Figure 2.1, MX86250 function block diagram. As shown in the diagram, the major function blocks are as follows : * * * * * * * * * 64 bit Graphics Co-processor Memory Controller PCI Bus Interface Unit Video Processor Media Port True color RAMDAC Dual Clock Synthesizer DDC/I2C/EEPROM interface ports VGA Controller The function block modules are connected with 64-bit buses. Multiple FIFOs buffer data flows within the tight pipeline structures allowing concurrent operations and maximum bandwidth. Figure 1 : MX86250 Function Block Diagram Graphics Processor Source FIFO ROP Destination FIFO Pattern MAP ALU Memory Controller DRAM Interface PCI Bus Interface Unit PCI BUS Command/Data FIFO Color Converter Video Processor Scaler & Filters DCLK Display Process Hardware Cursor Gx/Video FIFO Scaler & Filters Dual Clock Synthsizer MCLK Ture Color RAM DAC R.G.B DDC 12C EEPROM VGA Peripheral Interface Ports Gx Controller CRT Controller Attribute Controller Sequencer Medio Port VMI Connector P/N:PM0387 REV. 1.1, JUL 26, 1996 3 INDEX MX86250 2.2 64-BIT Graphics Co-processor The MX86250 Graphics Co-processor accelerates common Graphics User Interface drawing functions , including Bitblt, Rectangle Fill, Pattern Fill, Bresenham Line Draw, and Text Transfer. Hardware clipping and hardware cursor further reduce software driver overhead, including Bitblt, Rectangle Fill, Pattern Fill, Bresenham Line Draw, and Text Transfer. Hardware clipping and hardware cursor further reduce software driver overhead to the minimum. The Graphics Co-processor supports scrardware cursor further rr further reduce software driver overhead to the minimum. The Graphics Co-processor supports screen widths of 640, 800, 1024, 1152, 1280, 1600 and 2048. Pixel depth can be 8, 16, and 32 bits. The display memory size can be 1,2 or 4 megabytes. All Co-processor drawing operations are programmed with 32 bit registers in a linear address aperture. Pattern Map Buffer The most common Bitblt operation in Windows is the PatBlt which means painting a large window background using a brush which is an 8 by 8 pattern bitmap. Many GUI chips store the brush pattern bitmap in offscreen memory. During Patblt, the pattern are fetched repeatedly. To accelerate Patblt, the MX86250 has on-chip memory to store a full 8 by 8 pattern bitmap. Unlike others which can only store 8-bit pixels, The MX86250 can store pixel maps of 8, 16, and 32 bit pixels. This complete implementation of Pattern Map, enables the MX86250 to execute the Patblts at peak memory bandwidth using a long burst of page mode writes and thus achieving the best drawing performance. Text / Font drawing acceleration Drawing text characters or fonts are another very common Windows drawing operation. The fonts are monochrome bitmaps that get expanded into color pixel maps in the Graphics Co-processor. The MX86250 optimizes this process in several ways. Font bitmaps can be stored in system memory and transferred to the Co-processor for color expansion.The MX86250 provides a screen port to facilitate this memory to screen transfer. The screen port is mapped in a linear address aperture of 64K bytes. The monochrome font pixels are buffered in the Source FIFO so that concurrent operations are enabled for font transfer from system memory and color expansion in the Co-processor. The display driver can also cache font bitmaps in offscreen memory using the so called font-cache scheme. The MX86250 provides direct support of offscreen packed monochrome bitmap to color map expansion. This operation greatly accelerates the performance of font cache. Three Operand Bitblt The Graphics Co-processor executes Bitblt operations between three operands: the Source bitmap, the Destination bitmap, and the Pattern bitmap. There are 256 operations on bitmaps, called Raster Operations (ROP). An ALU with three operand inputs is implemented to execute any of the 256 RO P 's in a single cycle, unlike earlier generation GUI chips which used only two operands and implemented only 16 ROPs. This forced the software driver to decompose those 3-operand bitblt into two or three 2-operand BitBLTs significantly slowing down the drawing process. Source/Destination FIFOs The three inputs to the Bitblt ALU are from the Source FIFO, the Destination FIFO and the Pattern Map Buffer. The Source and Destination FIFO are 64 bit wide and 8 levels deep. They allow the fetch cycles for Source and Destination pixels to be run in page mode cycles. By having Destination FIFO, the MX86250 can run Destination read-modify-write operations in page mode reads followed by page mode writes which is substantially faster than the read-modify-write cycles in an EDO-DRAM based system. Windows 95 Direct Draw acceleration Windows 95 Direct Draw is aimed to turn the Windows GUI environment into a Game platform with high speed sprite animation. The key to sprite animation is Transparent Blt. The MX86250 implements a flexible Color Key mechanism to enable high speed Transparent Blt. A Transparent Blt writes to screen a source bitmap, that is, a sprite, which is in an irregular shape such as a cartoon P/N:PM0387 REV. 1.1, JUL 26, 1996 4 INDEX MX86250 figure. The background pixels which should not be overwritten are coded in the special Key color. The Color Compare function block in the Graphics Co-processor checks each pixel against the Key color. If a match is found, the pixel is not written, preserving the background around the sprite. Thus, an irregular shape is BLTed using a fast rectangle draw. In the MX86250, the Color Key can be in the Source or the Destination bitmap. Transparent Blt uses Source Color Key. The Destination Color Key can be used to protect screen areas. A mask register is defined to allow the key color be a range of color values instead of a single value. The Memory Controller generates all DRAM cycles. Its logic is carefully designed to optimize DRAM cycle timing parameters. For example, the DRAM entry cycle which is the time from RAS precharge to the end of first CAS cycle is optimized to the minimum of 4 clock cycles, versus the commonly seen 5 or 6 clock cycles in other GUI chips. Another example is that of EDO DRAM read cycle. The MX86250 eliminates the one extra clock cycle at the end of page mode cycles. Unified Memory Architecture The MX86250 fully supports the VESA Unified Memory Architecture (VUMA) standard. The Memory Controller implements the VUMA standard RQ/GNT state machine which supports two request priorities. Bus parking is provided to minimize bus switch overhead. DRAM read and write operations in UMA mode can have programmable number of wait states to accommodate the wide variation in main system DRAM module access speed. In addition, the DRAM interface drivers have programmable drive strength to work with wide range of DRAM interface loading on system motherboards. 2.3 Memory Controller The MX86250 Memory Controller module interfaces to the frame buffer DRAM chips which can operate in either fast page mode, or Extended Data Out (EDO) mode. The frame buffer size can be 1, 2, or 4 Megabytes. Industry standard 256K by 4, by 8, or by 16 DRAM chips are supported. The Memory Controller performs the page mode cycle in either 2 clock cycle or 1 clock cycle, depending on the DRAM types being used. The highest bandwidth is delivered using -50 EDO DRAM with 20 ns page cycle time and a 50 MHz memory clock, yielding a 400MB peak bandwidth. The MX86250 is capable of even higher Memory clock speed. As faster EDO DRAM (-35 with 15ns page mode cycle time) enters volume production, the MX86250 will deliver 533 MB/sec bandwidth which is comparable to premium priced DRAMs such as 66 Mhz SGRAM / SDRAM, or RAMBUS RDRAM. The center of the Memory Controller is an intricate arbiter which receives memory access requests from the Graphics Co-processor for Bitblt cycles, the Display controller for screen fetch, the Video Processor for video playback, the PCI Bus interface for CPU access, the Hardware Cursor for cursor bitmap fetch, and the DRAM refresh cycle request. The arbiter allocates memory cycles according to priority. For example, the Display Processor has higher priority than the Graphics Co-processor. A 32-level 64-bit FIFO is implemented to buffer the pixels fetched from display memory for the screen refresh and video playback. The FIFO entries can be flexibly allocated between three different processors: Graphics, Video line 1 and Video line 2. This flexibility works to optimize performance across various screen resolutions and video playback operations. 2.4 PCI Bus Interface Unit The MX86250 Bus Interface Unit (BIU) implements a glueless connection to industry standard PCI local bus which is compliant with Windows 95 Plug'n'Play requirement. PCI bus speed can be up to 33 MHz. For peak transfer rate between host CPU and the MX86250, zero wait state PCI burst cycles are supported. The resultant 133 MB per second bandwidth greatly enhances the performance level of Graphics intensive software such as Windows GUI and AutoCAD that do lots of direct accesses to video memory. The BIU has an 8 level command and data FIFOs to buffer host transfers and enables concurrent operations of the host CPU, the graphics engine and the Video Processor. The PCI Rev. 2.1 disconnect and retry protocol is fully supported eliminating the delays of host CPU polling for BIU FIFO status. P/N:PM0387 REV. 1.1, JUL 26, 1996 5 INDEX MX86250 2.5 Video Processor The MX86250 Video Processor accelerates the playback of AVI or MPEG video decoded by a software Codec such as Cinepak, Indeo, or MPEG-1. Profiling of the task load showed that about one third time each is spent in decompression, color conversion and pixel transfer to screen. The Video Processor implements the color conversion and pixel transfer in hardware, leaving only the decompression task to CPU. Thus, the video play frame rate which used to be 8 to 10 fps from software Codec is approximately tripled to the full motion rate of 30 fps by the MX86250. Video clips are typically in QCIF or CIF format which are relatively small when viewed on the SVGA display. It is very desirable to scale up the video window to at least 640x480 or even full screen at 1024x768. The scale up can be just duplicating the pixels (Zoom) which produces blocky pictures. In high end broadcast quality video processing, a smoothing filter is typically used to remove the blocky artifacts. The MX86250 Video Processor implements both Scaler and smoothing Filters so that full motion video can play in full screen without degradation. Direct Draw feature support The Video Processor fully support Windows 95 Direct Draw with features such as Chroma Key, Page flipping and Blending. The Chroma key is designed for Blue Screen video which is very useful in games where video sprites are employed. The new Indeo 4.0 transparency feature also makes heavy use of the Chroma key mechanism. The video window can be double-buffered to avoid tearing. The Video Processor executes page flipping in synchronization with Vertical blanking. A status bit is provided to inform software of the completion of page flipping. Edge Blending The MX86250 "edge blending" is an unique new feature. It is implemented to enhance the edge quality of Chroma keyed video sprites. DirectDraw does provide API calls which support the use of edge blending. The Blending feature provides 16 levels of alpha mixing of the video and graphics window. This can be used to do a very smooth dissolve or fade which are popular visual effects often used in edutainment titles. Horizontal and Vertical interpolation The Video Processor performs the filtering in both Horizontal and Vertical dimension. While most first generation Video chips only have one horizontal filter. The MX86250 provides three filters to fit the particular needs of different video decoders. The vertical interpolation filter further enhances the appearance of video images by eliminating staircasing diagonal lines and illegible text commonly seen in video played by 1st generation video chips. 2.6 Media Port The Media Port is a direct interface to MPEG and Video decoders. A MX86250 based graphics card can deliver very extensive multimedia functionality by fully utilizing the Media Port. An MPEG-1 decoder chip can be incorporated on board to deliver higher quality MPEG video. Video Front end such as the Philips SA7110 can be built in for Video Capture and live TV window. The Media Port can accept pixel data streams from either the pixel port or the PCI bus interface. The pixel data stream pass through a FIFO before it gets written into the frame buffer. A flexible decimation unit can be used to reduce the input video frame size - usually required for capturing camera input. The video window for Media Port video stream is also double buffered for anti-tearing. Interlaced video input can be captured in two ways: one field only, or converted to non-interlaced frame. Pixel Formats The Video Processor supports many pixel formats. The Video pixels can be in RGB formats such as KRGB1.5.5.5, RGB-5.6.5, XRGB-8.8.8. The KRGB has 1 key bit which works as a color key. More likely, the video pixels are in YUV format such as YUV-16 (4:2:2), YUV-8 (2:1:1), or YCbCr-16 (4:2:2). The YUV format pixel has a range of value from 0 to 255, while the YCbCr format pixel values are in the range of 16 to 240. P/N:PM0387 REV. 1.1, JUL 26, 1996 6 INDEX MX86250 VMI connector To support a wide variety of Video and MPEG decoders, the Media Port supports the VMI ( Video Module Interface) standard. The VMI specifies a 40-pin connector which, in addition to the VGA connector, contain an 8-bit YUV pixel bus and an 8-bit Host data bus. The pixel bus transfers 8-bit packed format YUV pixels from Video decoders to the Media port. The host bus transfers compressed MPEG data stream from the Media Port to the MPEG decoder chip. A small daughter card carrying the decoder chip plugs into the 40 and 26 pin connectors. To support the Philips 7110 chip 16-bit YUV pixel format. the MX86250 Media Port has a special mode where the VMI host bus pins are used for the upper 8 bits of YUV pixels. The PLL generate its output clock frequency based on two programmed values, the M and N value, and according to the following formula : fOUT = fREF * (M+2) / (N+2) * 2R where R is the 2 bit scale value. 2.9 Peripheral Interface ports The MX86250 has interface ports designed to support the VESA DDC monitor interface, the I2C channel, and serial EEPROM. VESA DDC standard The VESA DDC (Display Data Channel) standard specifies a two pin serial channel between the display monitor and the graphics controller. The display monitor sends its capability and configuration datum to the graphics controller chip for the display driver to set up video display mode accordingly. Windows 95 Plug'n'Play interface for display monitors is based on the DDC standard. The MX86250 provides fully compliant implementation of the DDC using the DD0 and DD1 pin. I2C and EEPROM support The I2C channel is also a two pin serial bus as defined by Philips. Many video components such as the SA7110 video decoder relies on the I2C channel. The MX86250 provides the SCK and SDA pin for interface to I2C channel. Some graphics cards are designed to store certain card configuration or setup information in non-volatile memory storage. The MX86250 can support such a card using serial EEPROM. The DD0 and DD1 pin can be programmed to form an interface to serial EEPROM chips. 2.7 True Color RAMDAC The MX86250 internal 24 bit RAMDAC provides three 256-entry 6-bit word color look-up table (LUT) RAMs feeding three 8-bit DACs for 8-bit per pixel modes. A clock doubled mode is also provided. A 24 bit LUT bypass is used in High Color (15/16 bits/pixel) and True Color ( 24 bits/pixel) modes. The RAMDAC works at pixel clock rate up to 160 MHz. Many high resolution display modes are possible at this high pixel clock rate. For example, with a 2 MB card, the following video mode provides flicker free displays, 1280x1024, 256 color, @80 Hz 1024x768, 64K color, @120 Hz 800x600, 16M color, @120 Hz 2.8 Dual Clock Synthesizers The MX86250 contains two phase locked loop (PLL) frequency synthesizers. They generate the dot clock (DCLK) for display logic and memory clock (MCLK) for memory controller and graphics engine. Each PLL scales the input reference frequency to a programmed clock frequency. The reference frequency comes from either the crystal oscillator across the XIN and Xout pin or from a clock input from XIN pin. P/N:PM0387 REV. 1.1, JUL 26, 1996 7 INDEX MX86250 2.10 Power-on Reset Strapping MD[3:0]: RASTCTRL[3:0] These 4 bits are used for RAS precharge/low timing controls. The selection is listed below : RASTCTRL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 RAS precharge (in MCLK) 3.5 3.5 3.5 2.5 2.5 2.5 1.5 1.5 3 3 3 2 2 2 Reserved Reserved RAS low (in MCLK) 5.5 4.5 3.5 4.5 3.5 2.5 3.5 2.5 6 5 4 5 4 3 Reserved Reserved MD10: MA9OUTSE This is used to select MA9 output pin if UMA is enabled. 0--MA9 output through WEB1 1--MA9 output through OEB MD11: Reserved MD12: EXTMCLK 0--Use internal MCLK 1--Use external MCLK. For UMA, external MCLK will come from CPU clock. MD13: EXTDCLK 0--Use internal DCLK 1--Use external DCLK MD14: FC8 0--16-bit or No Feature Connector 1--8-bit Feature Connector MD15: ENSTVW 0--Stereo View off. 1--Enable Stereo View. DD1 is used for stereo view control. DD1 is high for odd field, low for even field during interlaced display. For non-interlaced display, DD1 is always low. MD16: RETRYOFF 0--Enable Bus Retry. 1--Disable Bus Retry. MD17: CROMRETRYOFF 0--Enable disconnect function for Configuration and ROM accesses. 1--Disable disconnect function for Configuration and ROM accesses. MD[5:4]: DRAMCYC[1:0] DRAMCYC[1:0] 00 01 10 11 DRAM CYCLES 2 cycles Fast Page DRAM cycle 2 cycles EDO DRAM cycle 1 cycles EDO DRAM cycle Reserved MD6: DUALCAS 0--Dual WE DRAM 1--Dual CAS DRAM MD7: ENUMA 0--Disable UMA 1--Enable UMA MD8: Reserved MD9: Reserved P/N:PM0387 REV. 1.1, JUL 26, 1996 8 INDEX MX86250 2.11 Pin Description PCI Bus Interface Pins: Pin Name RSTB# Pin No. Type 178 I Description This input is PCI bus RESET#, it is an active low signal used to initialize the GUI to a known state. The trailing edge of this input loads the power on strapping inputs through MD0 to MD17. The power on strapping input pins each has an internally weakly pulled down resistor (about 50K Ohm). If a power on reset input status "0" is needed, then the corresponding pin doesn need an externally pulled up resistor. If a power on reset input status "1"is needed, then the corresponding pin must be pulled up by a 10K Ohm resistor. CPUCLK FRAMEB 167 173 I I This input is the PCI bus clock. It is an 1X clock of 33MHz. This input is FRAME#, it is low to indicate the GUI that a valid address is present on the PCI address bus and a New bus cycle or Burst bus cycles are starting. When sampling this signal low, GUI would latch the address and bus commands. IRDYB 170 I This input is Initiator RDY#, it is generated from an PCI Bus Master. When it is low, IRDYB indicates that the Initiator is able to complete the current bus transaction if and only if the TRDY# is also low. TRDYB 171 STO This output is Target RDY#, it is generated by GUI if the current bus cycle belongs to the GUI. When it is low, TRDY# indicates that the GUI is able to complete the current bus transaction which already targeted onto it if and only if the IRDY# is also low. It remains low until this current cycle ends, then goes into high for one PCI clock cycle, after that then goes into tri-state. DEVSELB 169 STO This output is DEVSEL#. When driven low, it indicates that GUI will respond to the current cycle. It remains low until this current cycle ends, then goes into high for one PCI clock cycle, after that then goes into tri- state. STOPB 172 STO This output is STOP#. When driven low, it indicates that GUI will request the current bus master to stop the current bus transfer. There are two configurations about this signal. One is called disconnect. Under this configuration, GUI will complete the current transaction as the last one. In this case, STOP# will be active at the same time that TRDY# is active. The other configuration is called retry. In this case, GUI just request the bus master to terminate the current cycle and retry again. TRDY# will not be generated in this cycle. Once asserted, it remains low until this current cycle ends then goes into high for one PCI clock cycle, after that then goes into tri-state. P/N:PM0387 REV. 1.1, JUL 26, 1996 9 INDEX MX86250 PCI Bus Interface Pins:(continued) Pin Name PAR Pin No. Type 174 TO Description This output is PAR. It is only driven during PCI bus master doing read accesses from GUI. When driven, it will provide an even parity across the AD[31:0], and C/BE#[3:0]. This signal is an tri-state output. INTRB 168 TO This output is INTA#. It is and interrupt request signal to system interrupt controller. This signal always hard wired to the PCI bus INTA# signal pin. It is an open drained output. This pin is typically unused in display subsystem design, but may be connected to IRQ9 via PCI configuration register. IDSEL 181 I This input is IDSEL. It is used as an Initialization Device Select during PCI bus Auto-configuration cycles. When high, it indicates that GUI is now selected as a target for PCI bus configuration cycles. CBE0# 180 I This multiplexed input is part of a PCI bus Command definition or a Byte Enable for byte lane 0. During address phase of a PCI bus transaction, it defines the Command. During data phase of a PCI bus transaction, it defines if byte lane 0 is engaged in the transfer or not. CBE1# CBE2# CBE3# 179 177 175 I I I This is bit 1 of bus command and byte enable. This is bit 2 of bus command and byte enable. This is bit 3 of bus command and byte enable. The PCI bus Commands supported are listed below: C\BE[3:0]# 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1010 1100 1101 1110 1111 P/N:PM0387 PCI bus Command Type (Interrupt Acknowledge) (Special Cycle) I/O Read I/O Write reserved reserved Memory Read Memory Write reserved reserved Configuration Read Configuration Write Memory Read Multiple (Dual Address Cycle) Memory Read Line Memory Write and Invalidate REV. 1.1, JUL 26, 1996 10 INDEX MX86250 PCI Bus Interface Pins:(continued) Pin Name AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 Pin No. Type 41 40 38 37 36 35 34 33 32 31 29 28 27 26 25 24 23 22 20 19 18 17 16 15 14 13 12 10 9 8 7 6 I/O Description AD[31:0] is the multiplexed Address and Data bus for PCI, which 32-bit wide. P/N:PM0387 REV. 1.1, JUL 26, 1996 11 INDEX MX86250 DRAM INTERFACE PINS: Pin Name RASB0 Pin No. Type 95 TO Description This output is RAS0#, it is the RAS address strobe for bank 0, i.e. the first 2MB of 4MB DRAM memory. Dual CAS or dual WE of fast page or EDO DRAM can be supported.In UMA interface, this output will be tristated if GUI is not granted to access the memory bus. RASB1 98 TO This output is RAS1#, it is the RAS address strobe for bank 1, i.e. the second 2MB of 4MB DRAM memory. In UMA interface, this output will be tristated if GUI is not granted to access the memory bus. CASB0 82 TO For dual CAS DRAM type configuration, this output is CAS0#. It is the CAS address strobe of byte lane 0. For dual WE DRAM type configuration, this output is WE0#, it is the WE# control signal of byte lane 0. In UMA interface, this output will be tristated if GUI is not granted to access the memory bus. CASB1 81 TO For dual CAS DRAM type configuration, this output is CAS1#. It is the CAS address strobe of byte lane 1. For dual WE DRAM type configuration, this output is WE1#, it is the WE# control signal of byte lane 1. In UMA interface, this output will be tristated if GUI is not granted to access the memory bus. CASB2 80 TO For dual CAS DRAM type configuration, this output is CAS2#. It is the CAS address strobe of byte lane 2. For dual WE DRAM type configuration, this output is WE2#, it is the WE# control signal of byte lane 2. In UMA interface, this output will be tristated if GUI is not granted to access the memory bus. CASB3 79 TO For dual CAS DRAM type configuration, this output is CAS3#. It is the CAS address strobe of byte lane 3. For dual WE DRAM type configuration, this output is WE3#, it is the WE# control signal of byte lane 3. In UMA interface, this output will be tristated if GUI is not granted to access the memory bus. P/N:PM0387 REV. 1.1, JUL 26, 1996 12 INDEX MX86250 DRAM INTERFACE PINS:(continued) Pin Name CASB4 Pin No. Type 101 TO Description For dual CAS DRAM type configuration, this output is CAS4#. It is the CAS address strobe of byte lane 4. For dual WE DRAM type configuration, this output is WE4#, it is the WE# control signal of byte lane 4. In UMA interface, this output will be tristated if GUI is not granted to access the memory bus. CASB5 102 TO For dual CAS DRAM type configuration, this output is CAS5#. It is the CAS ad dress strobe of byte lane 5. For dual WE DRAM type configuration, this output is WE5#, it is the WE# control signal of byte lane 5. In UMA interface, this output will be tristated if GUI is not granted to access the memory bus. CASB6 103 TO For dual CAS DRAM type configuration, this output is CAS6#. It is the CAS ad dress strobe of byte lane 6. For dual WE DRAM type configuration, this output is WE6#, it is the WE# control signal of byte lane 6. In UMA interface, this output will be tristated if GUI is not granted to access the memory bus. CASB7 104 TO For dual CAS DRAM type configuration, this output is CAS7#. It is the CAS address strobe of byte lane 7. For dual WE DRAM type configuration, this output is WE7#, it is the WE# control signal of byte lane 7. In UMA interface, this output will be tristated if GUI is not granted to access the memory bus. WEB0 94 TO For dual CAS DRAM type configuration, this output is WE0#. It is the WE# control signal of bank 0. For dual WE DRAM type configuration, this output is CAS0#, it is the CAS address strobe of bank 0. In UMA interface, this output will be tristated if GUI is not granted to access the memory bus. P/N:PM0387 REV. 1.1, JUL 26, 1996 13 INDEX MX86250 DRAM INTERFACE PINS:(continued) Pin Name WEB1 Pin No. Type 97 TO Description For dual CAS DRAM type configuration, this output is WE1#. It is the WE# control signal of bank 1. For dual WE DRAM type configuration, this output is CAS1#, it is the CAS address strobe of bank 1. In UMA interface, this output will be tristated if GUI is not granted to access the memory bus. If GUI is granted, this has the above function when MA9OUTSE is 1. If MA9OUTSE is 0, it is the MA9, which is necessary for asymmetrical DRAM. OEB 99 TO This output is OE#, it is the OE# control signal for both banks of DRAM. In UMA interface, this output will be tristated if GUI is not granted to access the memory bus. If GUI is granted, this has the above function when MA9OUTSE is 0. If MA9OUTSE is 1, it is the MA9, which is necessary for asymmetrical DRAM. MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 83 84 85 87 88 89 90 91 92 78 77 76 75 74 72 71 70 I/O MD[7:0] is the DRAM data bus of memory plane 0 of bank 0 or bank 1. In BIOS ROM accesses, these are the data inputs[7:0] of external ROM. They are also served as power-on strapping inputs. TO The outputs MA[8:0] is the DRAM memory address bus for both banks. It is used to pass the RAS address and CAS address to DRAMs. In UMA interface, these outputs will be tristated if GUI is not granted to access the memory bus. P/N:PM0387 REV. 1.1, JUL 26, 1996 14 INDEX MX86250 DRAM INTERFACE PINS:(continued) Pin Name MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 Pin No. Type 69 68 67 66 64 63 62 61 60 59 58 56 55 54 53 52 51 50 49 47 46 45 44 43 105 106 107 108 109 110 111 112 I/O MD[39:32] is the DRAM data bus of memory plane 4 of bank 0 or bank 1. I/O MD[31:24] is the DRAM data bus of memory plane 3 of bank 0 or bank 1. In BIOS ROM accesses, MD[31:16] are the address outputs[15:0] for external ROM. I/O MD[23:16] is the DRAM data bus of memory plane 2 of bank 0 or bank 1. MD[17:16] are also used as power-on strapping inputs. I/O Description MD[15:8] is the DRAM data bus of memory plane 1 of bank 0 or bank 1. They are also served as power-on strapping inputs. P/N:PM0387 REV. 1.1, JUL 26, 1996 15 INDEX MX86250 DRAM INTERFACE PINS:(continued) Pin Name MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 Pin No. Type 114 115 116 117 118 119 120 121 122 124 125 126 127 128 129 130 131 133 134 135 136 137 138 139 I/O MD[63:56] is the DRAM data bus of memory plane 7 of bank 0 or bank 1. I/O MD[55:48] is the DRAM data bus of memory plane 6 of bank 0 or bank 1. I/O Description MD[47:40] is the DRAM data bus of memory plane 5 of bank 0 or bank 1. P/N:PM0387 REV. 1.1, JUL 26, 1996 16 INDEX MX86250 UMA Interface Pins: Pin Name SMURQB Pin No. Type 182 O Description This is the MREQ# signal for VESA UMA interface. GUI uses this signal to request memory accesses on UMA. SMGNTB 183 I This is the MGNT# signal from VESA UMA interface. GUI will drive DRAM interface signals when this signal is active in UMA configuration. ROM BIOS Interface Pins: Pin Name ROMOEB Pin No. Type 42 O Description This output is ROMOE#. It may be connected to either one or both of the BIOS ROM chip select and output enable pins directly. Internal VCG Related Interface Pins: Pin Name XI Pin No. Type 157 I Description This input is used as a Reference Frequency Input for internally implemented oscillator. An external crystal or oscillator of 14.318Mhz may be used. If an external crystal is used, it must be connected between XIN and XOUT. If an external oscillator is used, it must connect to XIN. In this case, the XOUT must be left open. XO 158 O This is used as a Reference Frequency output for internally implemented oscillator. If an external crystal is used, it must be connected between XIN and XOUT. If an external oscillator is used, the XOUT must be left open. P/N:PM0387 REV. 1.1, JUL 26, 1996 17 INDEX MX86250 Internal RAMDAC Related Interface Pins: Pin Name SVREF Pin No. Type 4 I Description This pin is the Voltage Reference of 1.2V for internal DAC and Monitor Sence logic. It must be connected with a 0.1u capacitor to AVCC of RAMDAC. SCOMP 161 I This pin is the Compensation input for internal DAC. It must be connected with a 0.1u capacitor to AVCC of RAMDAC. SIREF SR 2 206 I O This pin is the Current Reference. This pin is the analog output of the pixel color Red component to monitor. It has a voltage level of 0.0V(blank) to 0.7V(full scale) when terminated with 75 ohm double loads. SG 207 O This pin is the analog output of the pixel color Green component to monitor. It has a voltage level of 0.0V(blank) to 0.7V(full scale) when terminated with 75 ohm double loads. SB 208 O This pin is the analog output of the pixel color Blue component to monitor. It has a voltage level of 0.0V(blank) to 0.7V(full scale) when terminated with 75 ohm double loads. Media Port and Feature Connector Related Interface Pins: Pin Name P0 P1 P2 P3 P4 P5 P6 P7 Pin No. Type 141 142 143 144 145 146 147 148 For 8-bit Feature Connector or VAFC, this is a bidirectional pixel data bus. When EVIDEO# is low, it functions as inputs. The pixel data from external display or video card will be passed to the internal RAMDAC for display. If EVIDEO# is high, the internal RAMDAC uses pixel data internally generated for display. In this case, if PA output control for DPMS, which is defined in bit 6 of register 3?5/26, is set to normal operation, GUI will drive out pixel data. Otherwise, it will tristate the output. If VMI is used, P[7:0] is the video data inputs. This chip supports SAA7110 video decoder and CL480 MPEG decoder interfaces. For SAA7110 interfaces, P[7:0] is the lower byte of the 16-bit video data inputs. For CL480 interfaces, it's the 8-bit video data inputs. P/N:PM0387 REV. 1.1, JUL 26, 1996 Description P[7:0] is the pixel or video data bus from/to external Feature Connector or Video Module Interfaces. IO 18 INDEX MX86250 Media Port and Feature Connector Related Interface Pins:(continued) Pin Name P8 P9 P10 P11 P12 P13 P14 P15 Pin No. Type 187 188 190 191 192 193 194 195 IO IO IO IO IO IO IO IO For VAFC or 16-bit Feature Connector, P[15:8] functions as pixel output or video input. When EVIDEO# is low, it is used for video input, which will be passed to the internal RAMDAC for display. If EVIDEO# is high, the internally generated pixel data will be driven out to video card if PA output control for DPMS is set to normal operation. If VMI is used, P[15:8] is used as the host data bus, which is bidirectional. Through this bus, CPU can access the VMI module. For SAA7110 interfaces, P[15:8] is the higher byte of the 16-bit video data inputs. For CL480, it's the 8-bit host data bus, which is inputs in read cycles, and outputs in write cycles. PCLK 150 IO This is the pixel clock input/output pin. For 8-bit Feature Connector, it is an input when EVIDEO# is low. In this case, it is used for internal RAMDAC display. When EVIDEO# is high, the internally generated pixel clock is driven out through this pin. For VAFC, it's always an pixel clock output. The internal pixel clock for RAMDAC is also driven to this pin. For VMI connection, PCLK is always put in tri-state. RAMDAC use internal pixel clock for display. If external DCLK is used, only 8-bit Feature Connector configuration is allowed, i.e. other video interfaces are not applicable. **** Shouls be divided by 8 SEVIDEOB 151 I In test mode, this is the DCLK output from internal VCG. This is the EVIDEO# pin used as bidirection control for 8-bit Feature Connector or VAFC interfaces. When set to 1, GUI will drive P[15:0], BLANK#, HSYNC, VSYNC and PCLK to the Feature Connector. When set to 0, all of these signal pins are tri-stated. If video interface is enabled, i.e. either SAA7110 or CL480 is used for video data input, this pin loses its function. EXTVCLK 152 I This is the video clock input pin for video interface and VAFC. If external DCLK is used, it is taken for external pixel clock input. In that case, video interface and VAFC are not allowed. Description P[15:8] is the pixel data bus from/to external Feature Connector or host data bus from/to VMI. P/N:PM0387 REV. 1.1, JUL 26, 1996 19 INDEX MX86250 Media Port and Feature Connector Related Interface Pins:(continued) Pin Name BLANKB Pin No. Type 154 IO Description This is a multi-function pin. For 8-bit Feature Connector or VAFC, when EVIDEO# is high, the internal BLANK# signal is used to control RAMDAC display. In this case,it is an output pin if the BLANK control for DPMS, which is defined in bit [1:0] of register 3?5/26, is not set to 11. Otherwise, it will be tri-stated. When EVIDEO# is set to 0, it's an input from Feature Connector. GUI uses it to control RAMDAC display. For VMI or SAA7110, it's the HREF input. And for CL480 it's the HSYNC# input. In either case, it indicates that video data of a scanline is coming in. HSYNCB 155 TO It's the HSYNC# output pin, which is the horizontal sync to analog monitor. For 8bit Feature Connector or VAFC, it is enabled when EVIDEO# is high and HSYNC control for DPMS, which is defined in bit [3:2] of register 3?5/26, is set to value other than 11. Otherwise, it is tri-stated. But if either SAA7110 or CL480 is select, it is enabled also. VSYNCB 156 TO It's the VSYNC# output pin, which is the vertical sync to analog monitor. For 8-bit Feature Connector or VAFC, it is enabled when EVIDEO# is high and VSYNC control for DPMS, which is defined in bit [5:4] of register 3?5/26, is set to value other than 11. Otherwise, it is tri-stated. But if either SAA7110 or CL480 is select, it is enabled also. L4VS 198 IO If external VCG is selected, this pin is used as one of the MCLK select output, MCSEL1. MCSEL[2:0] is used to select MCLK frequency from external VCG. If internal VCG is used, it is an input pin for video interface. It's the VREF for VMI, VS for SAA7110 and VSYNC# for CL480. Either one indicates that it's the frame start of input video data. SCK 5 IO It's the I2CCLK input/output pin for both SAA7110 interface or DDC2 monitor control. As an input, the I2C CLK value can be monitored by reading bit 2 of the memory-mapped register port at offset 31C or bit 2 of the I/O register at 3?5/50. To generate clock pulses, software can just program either bit 0 of the above memorymapped register or bit 5 of the IO register at 3C4/1E. If 0 is programmed, this pin is pulled low. If 1 is programmed, this pin is tri-stated. With the external pull-up, it makes I2 CCLK go to high state. In this way, clock pulses are generated. P/N:PM0387 REV. 1.1, JUL 26, 1996 20 INDEX MX86250 Media Port and Feature Connector Related Interface Pins:(continued) Pin Name L4SDA Pin No. Type 204 IO Description This is a multi-function pin. If external VCG is selected, this pin is used as of the MCLK select output, MCSEL2. Otherwise, it is the serial data input/ouput pin for I2C bus. As an input, it can be monitored by reading bit 3 of the memory-mapped register at offset 31C, or of the I/O port at 3?5/50. To generate data, software can program either bit 1 of the above memory-mapped register or bit 6 of the I/O register at 3C4/1E. L4HSEL0 200 O This is a dual-function pin. If external DCLK is selected, this pin is used as one of the DCLK select output, VCKSEL0. VCKSEL[3:0] is used to select DCLK frequency from external VCG. Otherwise, it is used as HA0 for VMI or HSEL0 for CL480. HA[2:0] and HSEL[2:0] are the host address bus for VMI and CL480 individually. L4HSEL1 202 O This is a dual-function pin. If external DCLK is selected, this pin is used as one of the DCLK select output, VCKSEL1. Otherwise, it is used as HA1 for VMI or HSEL1 for CL480. L4HSEL2 202 O This is a dual-function pin. If external DCLK is selected, this pin is used as one of the DCLK select output, VCKSEL2. Otherwise, it is used as HA2 for VMI or HSEL2 for CL480. L4RWB 203 O This is a dual-function pin. If external DCLK is selected, this pin is used as one of the DCLK select output, VCKSEL3. Otherwise, it is used as R/W# for VMI or CL480. In that case, it controls the host read/write with them. For read cycles, it is driven high, for write cycles, it is driven low. L4DSB 197 O It is a dual-function pin. If external VCG is selected, it is used as one of the MCLK select output, MCSEL0. Otherwise, it is used as DS# for VMI or CL480. GUI pulls it low to select VMI target or CL480 for read/write operation. CFLEVEL 153 I It is the CFLEVEL input from CL480 or ODD from SAA7110 or the MCLK input if external MCLK is selected. As the CFLEVEL from CL480, it indicates that the CL480 Coded Data FIFO for compressed data is going to be exhausted. GUI will generate the interrupt signal to inform the software to put more compressed data into CL480. When used as the ODD signal from SAA7110, it is an odd/even field indication for interlaced video. When high, it is odd field, otherwise, even field. GUI uses this to determine the memory location for incoming video data. P/N:PM0387 REV. 1.1, JUL 26, 1996 21 INDEX MX86250 Media Port and Feature Connector Related Interface Pins:(continued) Pin Name DD0 Pin No. Type 184 IO Description It is a dual-function pin. If CL480 or VMI interface is enabled, it is the DTACK# input, which is the host data acknowledge from them. When set to 0, it indicates that CL480 or VMI target is ready for data receiving or output. GUI can thus complete the cycle. If not the above case, it is a general data I/O pin. It can be read through bit 0 of IO port 3?5/50. As an output, it's in tristate normally. Write to I/O register 3C2, 3C5/1D or 3C5/1E will enable it. Bit 3 of 3C5/1E is selected as its output value. DD1 185 IO It is a dual-function pin. When Stereo View is enabled, it is used as the stereo view control output. During interlaced display, it is high for odd field and low for even field. For non-interlaced display, it is always driven low. It is also a general data input/output pin. As an input, it can be read through bit 1 of IO port 3?5/50. To use it as an output, I/O registers 3C2, 3C5/1D or 3C5/1E should be written. It then leaves tristate and select bit 4 of 3C5/1E as its output value. STB 186 O This is the data write strobe for external devices when DD[1:0] are used as general data input/output pins. It is used to latch DD[1:0] driven by GUI. It is high when I/O registers 3C2, 3C5/1D or 3C5/1E is written or power-on reset completes. If external VCG is used, it is used to latch VCKSEL[3:0]. The external VCG will use these values to generate expected frequencies of DCLK. STRDB 196 O This is the data read enable for external devices when DD[1:0] are used as general data input/output pins. The external devices should drive DD[1:0] when this signal is low. Otherwise, put them to tri-state. P/N:PM0387 REV. 1.1, JUL 26, 1996 22 INDEX MX86250 POWER PINS: PIN NAME VDDP GNDP VDD GND AVDD AVSS PIN TYPE PIN NO. 11,57,123, 164,199, 21,48,65,73,100,113,140, 149,176, 189 30,93,165 39,86,96,132,166 1,159, 163 3,160, 162,205 DRIVE(ma) C_LOAD(pf) - P/N:PM0387 REV. 1.1, JUL 26, 1996 23 INDEX MX86250 2.12 PINOUT CONFIGURATION XI XO VDD GND SCOMP GND VDD VDDP VDD GND CPUCLK INTR DEVSELS IRDYB TRDYB STOPB FRAMEB PAR CBEB3 GNDP CBEB2 RSTB CBEB1 CBEB0 IDSEL SMURQB SMGNTB DD0 DD1 STB P8 P9 GNDP P10 P11 P12 P13 P14 P15 STRDB L4DSB L4VS VDDP L4HSEL0 L4HSEL1 L4HSEL2 L4RWB L4SDA GND SR SG SB 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 VSYNCB HSYNCB BLANKB CFLEVEL EXTVCLK SEVIDEOB PCLK GNDP P7 P6 P5 P4 P3 P2 P1 P0 GNDP MD63 MD62 MD61 MD60 MD59 MD58 MD57 GND MD56 MD55 MD54 MD53 MD52 MD51 MD50 MD49 VDDP MD48 MD47 MD46 MD45 MD44 MD43 MD42 MD41 MD40 GNDP MD39 MD38 MD37 MD36 MD35 MD34 MD33 MD32 MX86250 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 CASB7 CASB6 CASB5 CASB4 GNDP OEB RASB1 WEB1 GND RASB0 WEB0 VDD MA8 MA7 MA6 MA5 MA4 MA3 GND MA2 MA1 MA0 CASB0 CASB1 CASB2 CASB3 MD0 MD1 MD2 MD3 MD4 GNDP MD5 MD6 MD7 MD8 MD9 MD10 MD11 GNDP MD12 MD13 MD14 MD15 MD16 MD17 MD18 VDDP MD19 MD20 MD21 MD22 VDD SIREF GND SVREF SCK AD31 AD30 AD29 AD28 AD27 VDDP AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 GNDP AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 VDD AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 GNDP AD1 AD0 ROMOEB MD31 MD30 MD29 MD28 MD27 GNDP MD26 MD25 MD24 MD23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 P/N:PM0387 REV. 1.1, JUL 26, 1996 24 INDEX MX86250 MACRONIX INTERNATIONAL CO., LTD. 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